1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and more particularly to a method of manufacturing a semiconductor device with circuit-element-isolation trenches on a substrate.
2. Description of the Related Art
With the recent increase of integration and operating speed of semiconductor devices, various technologies have been advanced remarkably to miniature individual circuit elements to be loaded on each semiconductor device, and application of the LOCOS (Local Oxidation of Silicon) isolation using a silicon nitride film for electrically isolating individual circuit elements has increasingly been limited.
Consequently new element isolation technologies utilizing trenches have been developed. For example, Japanese Patent Laid-Open Publication No. Sho60-124840 proposed a technology of forming trenches, filling an insulation film in the trenches and then annealing at a temperature equal to or below a melting point of a substrate.
Another solution was proposed by a paper "An Optimized Densification of the Filled Oxide for Quarter Micron Shallow Trench Isolation" presented in Symposium on VLSI technology Digest Technical Papers 1996 by Han Sim Lee, et al. This technology will now be described with reference to FIG. 4 of the accompanying drawings of the present specification.
As shown in FIG. 4, a number of predetermined trenches 104 are formed on a silicon substrate 101, and then a thermal oxide film 102 is formed on the inside walls of the trenches 104, whereupon a silicon oxide film 105 is filled in the trenches 104 by low pressure chemical vapor deposition (hereinafter also called LP-CVD) and is leveled by chemical and mechanical polishing (hereinafter called the CMP process).
In their paper, Lee, et al. disclosed that densification of the silicon oxide film, namely, resistance to wet etching was achieved by annealing at a lower temperature in a water-vapor ambient.
Lee, et al. also pointed out that since the inside walls of the trenches were oxidized, stresses occurred in the trenches to cause crystalline faults.
However, in this conventional technology, since the silicon oxide film used to fill the trenches by CVD was inadequately densified, the wet etching rate was great. Consequently, as shown in FIG. 4, after leveling by the CMP method, pits 106 occurred in the film filled in the trenches or a non-illustrated slit occurred centrally in the individual trench.
In the meantime, in order to improve the foregoing inconvenience, as an example, it is necessary to densify the silicon oxide film as by annealing at a high temperature equal to or higher than 1200.degree. C. But if this technique was adopted, large thermal stresses would have occurred in the substrate to cause slippage and/or crystal faults.
Yet in this conventional technology, since densification by annealing is carried out at a low temperature, the inside walls of the trenches are oxidized so that large stresses occur in the trenches, thus causing faults in the substrate.